Dynamic element matching in a/d converters

ABSTRACT

An A/D converter stage including an A/D sub-converter connected to a D/A sub-converter ( 12 ) provides dynamic element matching. This is accomplished by forcing ( 24 ) the comparators (COMP 1 -COMP 7 ) of the A/D sub-converter to generate a scrambled thermometer code.

TECHNICAL FIELD

[0001] This invention relates to analog-to-digital converters (A/Dconverters), and in particular to dynamic element matching inmulti-stage A/D converters, such as pipeline, sub-ranging, cyclic andmulti-bit delta-sigma A/D converters.

BACKGROUND

[0002] The maximum achievable accuracy-speed performance of any A/Dconverter is limited by non-ideal effects associated with its buildingblocks. Typically, the performance is limited by settling time, finiteamplifier gain, and/or component mismatch. When designing high-speed,high-accuracy A/D converters, these limitations impose stringent demandson building blocks, leading to prolonged design time and lower yield.

[0003] In many cases dynamic element matching can be used to reduce thenegative impact of the non-ideal effects by randomizing the errors. Forexample, references [1-3] describe scrambling of the thermometer codebus to achieve dynamic element matching. The non-linearity of the A/Dconverter then appears as a random noise which increases the noise floorinstead of producing harmonic distortion and intermodulation.

[0004] A problem with the prior art dynamic element matchingimplementations is that extra logic is required on the time criticalthermometer code bus. This results in an extra signal delay, which has anegative impact on the maximal achievable sample rate.

SUMMARY

[0005] An object of the present invention is to provide dynamic elementmatching for A/D converters without this extra signal delay.

[0006] This object is achieved in accordance with the attached claims.

[0007] Briefly, the present invention implements dynamic elementmatching outside of the thermometer code bus by forcing the comparatorsof the A/D sub-converter of a stage to produce a scrambled thermometercode. This eliminates the extra delay on the thermometer code bus,thereby increasing the attainable sample rate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The invention, together with further objects and advantagesthereof, may best be understood by making reference to the followingdescription taken together with the accompanying drawings, in which:

[0009]FIG. 1 is a block diagram of a typical pipeline A/D converter;

[0010]FIG. 2 is a block diagram of a typical stage of the A/D converterin FIG. 1 with conventional scrambling;

[0011]FIG. 3 is a diagram illustrating timing of essential controlsignals in the A/D converter stage in FIG. 2;

[0012]FIG. 4 is a block diagram of an exemplary embodiment of an A/Dconverter stage in accordance with the present invention;

[0013]FIG. 5 is a diagram illustrating timing of essential controlsignals in the A/D converter stage in FIG. 4;

[0014]FIG. 6 illustrates an exemplary scrambling unit implemented as abutterfly network;

[0015]FIG. 7 illustrates an exemplary embodiment of athermometer-to-binary converter suitable to be used in connection withthe present invention;

[0016]FIG. 8 illustrates another exemplary embodiment of athermometer-to-binary converter suitable to be used in connection withthe present invention;

[0017]FIG. 9 is a timing diagram illustrating settling times forthreshold level errors due to scrambling;

[0018]FIG. 10 illustrates an exemplary embodiment of a comparator inputstage;

[0019]FIG. 11 is a timing diagram illustrating settling times forthreshold level errors due to scrambling in the embodiment of FIG. 10;

[0020]FIG. 12 illustrates an exemplary embodiment of a comparator inputstage based on switched capacitor threshold generation;

[0021]FIG. 13 illustrates an exemplary embodiment of a stage in amulti-bit delta-sigma A/D converter configured in accordance with thepresent invention; and

[0022]FIG. 14 is a flow chart illustrating the method in accordance withthe present invention.

DETAILED DESCRIPTION

[0023] In the following description the same reference designations willbe used for the same or similar elements.

[0024] The description below will primarily describe the presentinvention with reference to a pipeline A/D converter. However, it isappreciated that the same principles may also be used for othermulti-stage A/D converters, such as sub-ranging, multi-bit delta-sigmaor cyclic A/D converters (although a cyclic converter is not literally amulti-stage converter, for the purposes of this description it isconsidered a multi-stage converter, since it performs A/D conversion inseveral steps by reusing an A/D converter stage).

[0025]FIG. 1 is a block diagram of a typical pipeline A/D converter. AnN-bit analog-to-digital conversion is performed in two or more stages,each stage extracting {N_(l), N₂ . . . N_(k)} bits of informationrepresented by the digital words {d₁, d₂ . . . d_(k)}, where K is thenumber of pipeline stages. The first pipeline stage extracts the N₁ mostsignificant bits using an N₁-bit A/D sub-converter 10. Then theestimated value is subtracted from the analog input signal V_(in) byusing a D/A sub-converter 12 and an adder 14, leaving a residuecontaining the information necessary to extract less significant bits.Usually the residue is amplified by an amplifier 16 having a gain G₁ toestablish the appropriate signal range for stage 2. These steps arerepeated for all K stages, with the exception of the last pipelinestage, which does not need to produce an analog output and therefore hasno D/A converter, adder or amplifier, but only an A/D converter 10. Thedigital words {d₁, d₂ . . . dK} are then combined to form the digitaloutput word d_(out) in a unit 18 for time alignment and digitalcorrection of A/D sub-converter data.

[0026] In order to simplify the following description, it is assumedthat an A/D converter stage has a resolution of 3 bits. This number issufficiently small to be manageable, but is also large enough toillustrate the essential features of a general case.

[0027]FIG. 2 is a block diagram of a typical stage of the A/D converterin FIG. 1. A/D sub-converter 10 includes a number of comparatorsCOMP1-COMP7. One input terminal of each comparator is connected to acorresponding reference voltage V1-V7. These reference voltages areformed by a ladder of resistors R1-R8. During A/D conversion the otherinput terminal of each comparator receives the analog input signal (thesame signal to each comparator). The output signals from the comparatorscollectively form the digitized value in thermometer code. These signalsare forwarded to D/A sub-converter 12 over a thermometer code bus formedby lines T1-T7, where they are transformed into a corresponding analogvalue. This value is subtracted from the original analog value (whichhas been stored in a sample-and-hold circuit 20) in adder 14, and theresidual signal is amplified by a gain equal to 4 in gain element 16.The bits from the stage are extracted by a thermometer-to-binaryconverter 22, which converts the thermometer code into binary code,typically by finding the transition from 1 to 0 in the thermometer codeand looking up the corresponding position in a ROM to get the binarycode.

[0028] Dynamic element matching is often used to randomize the errors ofthe A/D converter. The randomization is obtained by interchanging, in apseudorandom manner, the elements whose inadequate matching generateunwanted spurious signals. In pipeline A/D converters this usually meansthat the elements in a D/A sub-converter 12 are to be interchanged by ascrambling unit 24 controlled by a pseudo random scramble code. Theinterchange is typically performed by scrambling the thermometer codebits produced by A/D sub-converter 10 before the signals are applied tothe D/A sub-converter. Such scrambling decorrelates D/A sub-convertererrors from the input signal. Thus, the errors now appear as randomnoise and not as a systematic error.

[0029]FIG. 3 is a diagram illustrating the timing of control signalsΦ_(s) and Φ_(h) that control A/D sub-converter 10 and D/A sub-converter12, respectively, in the A/D converter stage in FIG. 2. The A/Dsub-converter decision phase starts when control signal Φ_(s) goes down.However, D/A conversion in D/A converter 12 can not start at the sametime, due to the delays T_(comp) and T_(scr) introduced by thecomparators of A/D sub-converter 10 and scrambling unit 24,respectively. Furthermore, there is a safety margin T_(m) to ensurerepetitive settling of the succeeding D/A sub-converter independently ofthe comparator delays, which are not precisely known. Thus, the totaldelay before D/A conversion starts by Φ_(h) going high is:

T _(total delay) =T _(comp) +T _(scr) +T _(m)

[0030] However, the total delay should be as short as possible, since ashorter delay translates into a higher attainable sample rate.Furthermore, scrambling unit 24 is often implemented as a multi-layerbutterfly structure (an example will be described with reference to FIG.6). Each layer introduces a delay. Since the required number of layersin the butterfly structure increases with the number of extracted bitsper stage, this means that the delay T_(scr) will also increase forhigher resolution stages. As a typical example, the delay by each layermay be 0.2 ns, which for a 3 layer butterfly structure results in adelay T_(scr) of 0.6 ns. This may be compared to a typical delayT_(comp) of 0.6 ns and a margin T_(m) of 0.2 ns. Thus, the total delayin this example is 1.4 ns.

[0031]FIG. 4 is a block diagram of an exemplary embodiment of an A/Dconverter stage in accordance with the present invention. In thisembodiment scrambling unit 24 has been moved from the thermometer codebus to the “comparator threshold bus” formed by lines V1-V7. Duringscrambling lines V1-V7 (and thus the reference voltages) to comparatorsCOMP1-COMP7 are interchanged in accordance with a scramble code, therebyforcing A/D sub-converter 10 to produce a scrambled code on thethermometer code bus (since the analog input signal is the same on allcomparators, it does not matter which comparator is assigned a certainthreshold level).

[0032]FIG. 5 is a diagram illustrating the timing of control signalsΦ_(s) and Φ_(h) in the A/D converter stage in FIG. 4. Since scramblingunit 24 has been removed from the thermometer code bus, the total delayon the bus will now be:

T _(total delay) =T _(comp) +T _(m)

[0033] Since the comparators are still present in the converter, theconversion delay T_(comp) will still remain. Using the exemplary delayvalues above, there is a delay reduction of more than 40%. Thisreduction may be used to increase the attainable sample rate.

[0034]FIG. 6 illustrates an exemplary scrambling unit 24 implemented asa butterfly network. In this embodiment thresholds V1-V7 pass 3 switchlayers, which are controlled by a scramble code (9 bits in the example).If a code bit is “low”, the corresponding switch does not alter thesignals. On the other hand, if the bit is “high”, the switch willexchange the corresponding threshold pair. By providing differentscramble codes in a pseudo random fashion, it is possible to combine theswitches in the layers in different exchange combinations, therebyimplementing “scrambling”.

[0035] Since converter 22 will now receive a scrambled thermometer code(in the prior art the proper thermometer code was available), it has tobe slightly modified. A possible solution is to insert a de-scramblingunit between the (scrambled) thermometer code bus and converter 22. Thisde-scrambling unit may simply comprise the same butterfly network as inFIG. 6, but with reversed input and output sides. In this way the samescramble code may be used for both the scrambling and de-scramblingunit. The de-scrambled signals may then be converted to binary form in aconventional manner.

[0036] Another possibility is to implement converter 22 as a Wallacetree decoder (see [4]), as illustrated in FIG. 7. The Wallace treeincludes a number of interconnected full adders. At the first (top inFIG. 7) level each adder counts the number of “ones” at its inputs T1-T3and T4-T6, respectively, and outputs a 2-bit coded word s,c (sum andcarry). At the second level further full adders add the 2-bit words fromthe previous level and also add the remaining signal T7. This gives thebinary code b2,b1,b0 for a 3-bit converter.

[0037]FIG. 8 illustrates another exemplary embodiment of athermometer-to-binary converter suitable to be used in connection withthe present invention. This converter is suitable for a 4-bit A/Dsub-converter. The 3-bit converter of FIG. 7 is used as a buildingblock, and the outputs from two such blocks are combined as illustratedin FIG. 8. For higher resolutions the same principle, namely tointerconnect outputs from lower resolution converters, may be repeated.

[0038] Thus, the Wallace tree is a simple and compact structure toimplement thermometer-to-binary conversion. Due to the tree structure,the length of the signal propagation is short. It can also easily bepipelined, which means that it will never be a speed limiting factor inthe A/D converter.

[0039] Scrambling of thresholds causes transients on the threshold codebus. These transients need some settling time before stable levels areobtained. FIG. 9 is a timing diagram illustrating settling times forthreshold level errors due to scrambling. This diagram is applicable foran embodiment in accordance with FIG. 4. In such an embodiment thethresholds are forwarded to the comparators for direct comparison withthe analog signal. The comparator input could, for example, comprise adifferential stage of a pre-amplifier or an input to a latch, whichpreferably is regenerative. The top of FIG. 9 illustrates the clockphases Φ_(s) and Φ_(h) controlling the A/D and D/A sub-converter,respectively. The middle part of FIG. 9 illustrates an analog signal,and the bottom part illustrates the threshold settling error afterscrambling. Latching of the comparators is performed at the falling edgeof Φ_(s). Threshold scrambling is performed shortly after the risingedge of Φ_(h). As may be seen from the FIG. 9, more than half a clockperiod is available for scrambled threshold settling, since a scrambledthreshold does not have to be stable until the next latching instant.

[0040]FIG. 10 illustrates an exemplary embodiment of a comparator inputstage suitable for handling differential input signals. In thisembodiment the thresholds are sampled onto capacitors for use in thenext clock phase. The clock phases Φ_(s2) and Φ_(h2) correspond to Φ_(s)and Φ_(h), respectively, whereas Φ_(h1) is a slightly leading version ofΦ_(h).

[0041]FIG. 11 is a timing diagram illustrating settling times forthreshold level errors due to scrambling in the embodiment of FIG. 10.High signals Φ_(h2) and Φ_(s2) correspond to capacitor input switches incorrespondingly designated switch states in FIG. 10. A high signalΦ_(h1) corresponds to closed (conducting) switches designated by Φ_(h1)in FIG. 10. Since the thresholds are not sampled simultaneously withcomparator latching, there is still more than half a clock periodavailable for threshold settling. Thus, although the scrambledthresholds have not yet settled at the time of comparator latching (whenthe analog signal is compared to the previously sampled thresholds),these scrambled thresholds still have almost half a clock period tosettle before they are to be sampled at the next falling edge of Φ_(h2).

[0042] The present invention is not limited to threshold voltagesgenerated by resistance ladders. As a further example, FIG. 12illustrates an embodiment of a comparator input stage based on switchedcapacitor threshold generation. The figure illustrates the input stageof comparator i of a 3-bit single-ended A/D sub-converter. An adder addsa 3-bit scramble code to the 3-bit representation of the comparatornumber i, which represents the default threshold. The carry is ignoredin the addition. The resulting signal, when non-zero, forms a thresholdword wi, from which each bit controls a corresponding switch forselecting a reference voltage, either V_(ref+) or V_(ref−). During clockphase Φ_(h2) the selected reference voltages are forwarded to a weightedcapacitor array, which forms the scrambled threshold. In this embodimentscrambling is accomplished by circulating the default threshold code (inthe adder), and the pseudo-random scramble code determines the numberbit positions to circulate. Since a zero threshold word corresponds to athreshold level that is not used, a resulting zero code from the adderis replaced by the scramble code (this is accomplished by the switchafter the adder), which is non-zero (between 1 and 7 in the illustratedembodiment). The reason for this choice is that no threshold word fromthe adder will comprise the scramble code, since this would imply thatthreshold word 000 has been added, which is not a valid defaultthreshold word (threshold words vary between 1 and 7 in the illustratedembodiment).

[0043]FIG. 13 illustrates an exemplary embodiment of a stage in amulti-bit delta-sigma A/D converter configured in accordance with thepresent invention. The illustrated embodiment is a continuous timemulti-bit delta-sigma A/D converter with a continuous time filter 21,typically an integrator for implementing a lowpass delta-sigmaconverter, and clocked comparators and D/A sub-converter.

[0044] It is also possible to implement a discrete time converter, forexample by implementing the integrator as a switched capacitor filterand by having continuous time (non-clocked) comparators and D/Asub-converter. In this case Φ_(s) and Φ_(h) will control the integratorinstead.

[0045]FIG. 14 is a flow chart illustrating the method in accordance withthe present invention. Step S1 represents the start of a new sampleperiod. Step S2 scrambles the threshold levels. Step S3 samples theanalog input signal with scrambled comparator thresholds. Step S4converts the resulting scrambled thermometer code to binary code. Thenthe procedure returns to step S1 for the next sample period.

[0046] In the description above the A/D sub-converter comparatorthresholds were modified to implement scrambling of the thermometer codeoutside of the thermometer code bus. An alternative would be to modify(offset) the analog input signal to each comparator. Still anotherpossibility would be to adjust the internal comparator offsets.

[0047] The present invention makes it possible to randomize the D/Asub-converter errors without introducing any speed or dynamic rangepenalty. By randomizing errors, such errors in A/D-conversion turn outas noise rather than distortion and intermodulation. This is a greatadvantage in most radio systems, but also in many other applications.The invention can be used either stand alone or as a complement tocalibration for high performance A/D converters.

[0048] It will be understood by those skilled in the art that variousmodifications and changes may be made to the present invention withoutdeparture from the scope thereof, which is defined by the appendedclaims.

REFERENCES

[0049] [1] Ian Galton, “Digital Cancellation of D/A Converter Noise inPipelined A/D Converters,” IEEE Transactions on Circuits and Systems-II:Analog and Digital Signal Processing, Vol. 47, No. 3, March 2000.

[0050] [2] Todd L. Brooks, David H. Robertson, Daniel F. Kelly, AnthonyDel Muro, and Stephen W. Harston, “A Cascaded Sigma-Delta Pipeline A/DConverter with 1.25 MHz Signal Bandwidth and 89 dB SNR,” IEEE Journal ofSolid-State Circuits, Vol. 32, No. 12, December 1997.

[0051] [3] P. Rombouts and L. Weyten, “Dynamic element matching forpipelined A/D conversion,” 1998 IEEE International Conference onElectronics, Circuits and Systems. Surfing the Waves of Science andtechnology, vol. 2, Sep. 7-9, 1998, Portugal.

[0052] [4] F. Kaess, R. Kanan, B. Hochet and M. Declercq, “New EncodingScheme for High-Speed Flash ADCs”, 1997 IEEE International Symposium onCircuits and Systems, Jun. 9-12, 1997, Hong Kong.

1. A dynamic element matching method for a D/A sub-converter of an A/Dconverter stage, including the step of controlling comparators of an A/Dsub-converter to generate scrambled thermometer code.
 2. The method ofclaim 1, including the step of modifying comparator thresholds forgenerating said scrambled thermometer code.
 3. The method of claim 1 or2, including the step of de-scrambling said scrambled thermometer codebefore thermometer-to-binary code conversion.
 4. The method of claim 1or 2, including the step of Wallace tree decoding forthermometer-to-binary code conversion of said scrambled thermometercode.
 5. An apparatus for dynamic element matching in a D/Asub-converter of an A/D converter stage, including means for controllingcomparators of an A/D sub-converter to generate scrambled thermometercode.
 6. The apparatus of claim 5, including means modifying comparatorthresholds for generating said scrambled thermometer code.
 7. Theapparatus of claim 5 or 6, including means for de-scrambling saidscrambled thermometer code before thermometer-to-binary code conversion.8. The apparatus of claim 5 or 6, including a Wallace tree forthermometer-to-binary code conversion of said scrambled thermometercode.
 9. An A/D converter stage including an A/D sub-converter,including means for controlling comparators of said A/D sub-converter togenerate scrambled thermometer code.
 10. The A/D converter stage ofclaim 9, including means modifying comparator thresholds for generatingsaid scrambled thermometer code.
 11. The converter stage of claim 9 or10, including means for de-scrambling said scrambled thermometer codebefore thermometer-to-binary code conversion.
 12. The converter stage ofclaim 9 or 10, characterized by a Wallace tree for thermometer-to-binarycode conversion of said scrambled thermometer code.
 13. A multi-stageA/D converter including means for dynamic element matching, includingmeans for controlling A/D sub-converter comparators to generatescrambled thermometer code.
 14. The A/D converter of claim 13, includingmeans modifying comparator thresholds for generating said scrambledthermometer code.
 15. The A/D converter of claim 13 or 14, includingmeans for de-scrambling said scrambled thermometer code beforethermometer-to-binary code conversion.
 16. The A/D converter of claim 13or 14, including a Wallace tree for thermometer-to-binary codeconversion of said scrambled thermometer code.
 17. The A/D converter ofclaim 13 or 14, wherein said A/D converter is a pipeline A/D converter.18. The A/D converter of claim 13 or 14, wherein said A/D converter is acyclic A/D converter.
 19. The A/D converter of claim 13 or 14, whereinsaid A/D converter is a sub-ranging A/D converter.
 20. The A/D converterof claim 13 or 14, wherein said A/D converter is a multi-bit delta-sigmaA/D converter.